Trench MOS-gated power devices

The solution described completely eliminates the parasitic JFET associated with lateral channel DMOS, and places the MOS channels vertically to allow both channel and anode current flow to be unidirectional. This can be achieved by using a MOS gate formed on the walls of a trench which is etched into the Si substrate. The p-body region of the MOS gate is formed by an epitaxial layer grown on the n-drift substrate prior to trench formation. The n+ source contact can be formed so that it is self aligned to the trench. In addition to allowing closer cell spacing by elimination of the JFET effect, trench-MOS also allows for an increase in current density due to the geometrical advantage gained by placing the gate vertically in the Si