• DocumentCode
    2881921
  • Title

    A 1.5 µ CMOS gate array with configurable ROM and RAM

  • Author

    Ueda, Makoto ; Sakashita, K. ; Yonezu, R. ; Fujimura, Takashi ; Arakawa, Takeshi ; Asai, Satoshi ; Kuramitsu, Y.

  • Author_Institution
    Mitsubishi Electric Corp., Itamo, Japan
  • Volume
    XXVIII
  • fYear
    1985
  • fDate
    13-15 Feb. 1985
  • Firstpage
    126
  • Lastpage
    127
  • Abstract
    The use of 1.5μ CMOS technology to implement a 8000 equivalent gate array with double word line memory addressing on a 9.9×9.8mm2chip will be discussed. Describe, too, will be the implementation and operation of a 16b micro-processor with 1024b ROM and 256b RAM.
  • Keywords
    CMOS logic circuits; CMOS technology; Etching; Logic arrays; Logic design; Logic gates; Microprocessors; Read only memory; Read-write memory; Routing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1985.1156783
  • Filename
    1156783
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2881921