Title :
Postlayout simulation of FPGAs using verilog
Author :
Colley, Martin J.
Author_Institution :
Dept. of Comput. Sci., Essex Univ., Colchester, UK
Abstract :
Postlayout simulation has proved to be an invaluable tool both for research and teaching purposes, allowing the designer to observe the operation of the device without the need for complex test equipment. A further benefit is that from within the Cadence environment it is possible to probe and trace internal signals, allowing the input and outputs of the logic blocks to be monitored
Keywords :
VLSI; circuit CAD; digital simulation; field programmable gate arrays; hardware description languages; logic CAD; Cadence environment; FPGAs; internal signals; logic blocks; postlayout simulation; verilog;
Conference_Titel :
Software Support and CAD Techniques for FPGAs, IEE Colloquium on
Conference_Location :
London
