Title :
FPGA design with Mentor and Altera CAD software
Author :
White, Martin ; Waller, Marcus ; Dunnett, Graham ; Lister, Paul
Author_Institution :
Sch. of Eng., Sussex Univ., Brighton, UK
Abstract :
This paper is an overview of top-down design with Mentor and Altera CAD tools. It outlines the entire process of designing hardware from writing VHDL to mapping the design to an FPGA. Intermediate steps including synthesis, optimisation, function simulation, layout and partitioning are also discussed. The conclusion derives from our experiences
Keywords :
circuit layout CAD; circuit optimisation; field programmable gate arrays; hardware description languages; logic CAD; logic partitioning; Altera; CAD software; FPGA design; Mentor; VHDL; function simulation; layout; optimisation; partitioning; top-down design;
Conference_Titel :
Software Support and CAD Techniques for FPGAs, IEE Colloquium on
Conference_Location :
London
