Title :
A 2K × 9 dual port memory
Author :
Barber, F. ; Eisenberg, D. ; Ingram, G. ; Strauss, Michael ; Wik, Torsten
Author_Institution :
AT&T Bell Laboratories, Allentown, PA, USA
Abstract :
A 2K×9 CMOS dual port RAM linking asynchronous data between processor systems will be reported. Memory provides separate access ports and internally resolves conflicting access requests. Circuit combines a timed shared CMOS SRAM with logic to achieve a contention-induced error rate of less than 100 FITS.
Keywords :
CMOS logic circuits; CMOS process; Decoding; Logic arrays; Multiplexing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156787
