Problems in designing FET MMICs with low distortion

The specification of subsystems forming part of an analogue communication link include many criteria that have to be simultaneously satisfied including efficiency, gain, bandwidth, noise factor, compression point and 3rd order intermodulation intercept point. Some criteria, such as power dissipation and bandwidth, can be readily predicted. Others are more difficult to predict, such as noise and 3rd order intermodulation intercept point. The optimisation of a circuit for low intermodulation distortion is probably one of the most difficult aspects of circuit design. In this paper we address the issue of designing circuits with low distortion, concentrating on the difficulties involved. These difficulties include the selection of suitable simulator device models, the selection of a convenient characterisation technique, and the selection of a suitable topology and operating point. We begin by describing the various regions of FET behaviour and how the popular simulator models represent these. Next the issue of mathematical representation of FET behaviour for analysis, design and device characterisation purposes is addressed. Finally we present a discussion of some of the issues in designing linear and nonlinear circuits for low distortion