Title :
A 100ps 9K gate ECL masterslice
Author :
Ullrich, H. ; Brackelmann, W. ; Fritzsche, H. ; Wieder, A.
Author_Institution :
Siemens AG, Munich-Perlach, Germany
Abstract :
This paper will report on a 9K ECL array with a 99.6ps propagation delay. The chip is ECL 10K or 100K compatible, consumes 20W typical and has 256 logic pins plus 64 supply pins.
Keywords :
Delay effects; Energy consumption; Integrated circuit interconnections; Lead; Logic arrays; Logic devices; Logic functions; Programmable logic arrays; Switches; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156812
