Title :
An NMOS pipelined image processor using quaternary logic
Author :
Kameyama, Michitaka ; Hanyu, T. ; Esashi, M. ; Higuchi, T.
Author_Institution :
Tohoku University, Sendai, Japan
Abstract :
A 2MHz pipelined image processing chip designed with a 5μm NMOS process will be discussed. Multiple ion implant quaternary logic has been found to result in a 4-fold reduction in complexity compared to a conventional binary implementation.
Keywords :
Image processing; Impedance matching; Logic arrays; Logic design; MOS devices; Multiplexing; Multivalued logic; Pattern matching; Pipeline processing; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156822
