DocumentCode
2882653
Title
An NMOS pipelined image processor using quaternary logic
Author
Kameyama, Michitaka ; Hanyu, T. ; Esashi, M. ; Higuchi, T.
Author_Institution
Tohoku University, Sendai, Japan
Volume
XXVIII
fYear
1985
fDate
13-15 Feb. 1985
Firstpage
86
Lastpage
87
Abstract
A 2MHz pipelined image processing chip designed with a 5μm NMOS process will be discussed. Multiple ion implant quaternary logic has been found to result in a 4-fold reduction in complexity compared to a conventional binary implementation.
Keywords
Image processing; Impedance matching; Logic arrays; Logic design; MOS devices; Multiplexing; Multivalued logic; Pattern matching; Pipeline processing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1985.1156822
Filename
1156822
Link To Document