Title :
Differential split-level CMOS logic for sub-nanoseconds speeds
Author :
Pfennings, L. ; Mol, W. ; Bastiaens, J. ; van Dijk, Jan
Author_Institution :
Philips Research Labs., Eindhoven, Netherlands
Abstract :
This paper will discuss subnanosecond gate delays (0.8ns) obtained for complex logic gates designed with cascode-coupled NMOS-PMOS loads, differential logic NMOS trees, and interconnect lines with 2.4V swings.
Keywords :
Adders; CMOS logic circuits; DSL; Degradation; Delay; Implants; Integrated circuit interconnections; Testing; Threshold voltage; Transconductance;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156827
