• DocumentCode
    2882776
  • Title

    A programmable digital signal processor with 32b floating point arithmetic

  • Author

    Kershaw, R. ; Bays, L. ; Freyman, R. ; Klinikowski, J. ; Miller, Colin ; Mondal, Kamanashish ; Moscovitz, H. ; Stocker, W. ; Luan Tran ; Hays, W. ; Boddie, J. ; Fields, E. ; Garen, C. ; Tow, J.

  • Author_Institution
    AT&T Bell Laboratories, Allentown, PA, USA
  • Volume
    XXVIII
  • fYear
    1985
  • fDate
    13-15 Feb. 1985
  • Firstpage
    92
  • Lastpage
    93
  • Abstract
    A report on a programmable DSP with 32b floating point arithmetic, 32b data path, and an extensive 32b instruction set, implemented in 1.5μ NMOS technology, will be presented. The chip contains 155,000 transistors and operates at 16MHz.
  • Keywords
    Adders; Circuits; Digital signal processing; Digital signal processors; Floating-point arithmetic; Microprocessors; Packaging; Random access memory; Read only memory; Read-write memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1985.1156829
  • Filename
    1156829
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2882776