A Low Power Mobile Camera Processor Design with SubLVDS Interface

Author

Lee, Charng L. ; Hsiao, Kuang-Ting ; Chou, Min-Chung

Author_Institution

Sunplus Technol. Co., Ltd., Hsinchu

fYear

2006

fDate

26-28 April 2006

Firstpage

1

Lastpage

4

Abstract

A mega pixel image signal processor (ISP) with low voltage differential serial interface is presented. subLVDS interface has lower voltage swing and lower power consumption advantages over a normal LVDS interface. Both subLVDS driver and receiver are implemented in this ISP chip to reduce the I/O pin count. A synchronization layer is designed to cover both non-compressed and compressed image data transfer on the high-speed serial data link. This chip is designed with a pure logic process in 0.18 mum CMOS technology. The subLVDS driver can operate at a transfer rate up to 625Mbps

Keywords

CMOS image sensors; CMOS logic circuits; driver circuits; image processing; low-power electronics; microprocessor chips; 0.18 micron; CMOS technology; differential serial interface; high-speed serial data link; image data transfer; image signal processing; mega pixel image signal processor; mobile camera processor design; subLVDS driver; subLVDS interface; synchronization layer; synchronization start codes; CMOS logic circuits; CMOS technology; Cameras; Energy consumption; Image coding; Logic design; Low voltage; Pixel; Process design; Signal processing; Image signal processing; LVDS and subLVDS; synchronization start codes;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2006 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

1-4244-0179-8

Electronic_ISBN

1-4244-0180-1

Type

conf

DOI

10.1109/VDAT.2006.258111

Filename

4027483