VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization

Author

Song, Yang ; Liu, Zhenyu ; Ikenaga, Takeshi ; Goto, Satoshi

Author_Institution

Graduate Sch. of Inf., Production & Syst., Waseda Univ., Fukuoka

fYear

2006

fDate

26-28 April 2006

Firstpage

1

Lastpage

4

Abstract

A 1D full search variable block sizes motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the add operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is required to store the search area and then reduces 72.7% hardware cost of SRAM. The design is realized with TSMC 0.18mum 1P6M technology with a hardware cost of 67.6K gates. In typical working condition (1.8V, 25degC), a clock frequency of 266MHz can be achieved

Keywords

SRAM chips; VLSI; logic circuits; logic design; motion estimation; video coding; 0.18 micron; 1.8 V; 25 C; 266 MHz; H.264/AVC; VLSI architecture; control logic; single-port SRAM; variable block size motion estimation; Automatic voltage control; Costs; Employee welfare; Hardware; Logic; Motion estimation; Random access memory; Registers; Scheduling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2006 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

1-4244-0179-8

Electronic_ISBN

1-4244-0180-1

Type

conf

DOI

10.1109/VDAT.2006.258131

Filename

4027503