DocumentCode
2883181
Title
A 240K transistor CMOS array with flexible allocation of memory and channels
Author
Takahashi, Hiroki ; Sato, Seiki ; Goto, Gensuke ; Nakamura, T. ; Kikuchi, Hiroaki ; Shirato, Toru
Author_Institution
Fujitsu Laboratories, Ltd., Atsugi, Japan
Volume
XXVIII
fYear
1985
fDate
13-15 Feb. 1985
Firstpage
124
Lastpage
125
Abstract
A CMOS masterslice will be reported, covering the design of basic cells to accommodate both logic unit and memory cells, wiring channels allocated in discrete units and logic and memory blocks placed in arbitrary positions of a cell array. Implementation of a 16×16b parallel multiplier with 16b×64w SRAM and 16b×256w ROM will be compared.
Keywords
CMOS logic circuits; Laboratories; Large-scale systems; Latches; Logic arrays; Logic design; Logic gates; Random access memory; Read only memory; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1985.1156853
Filename
1156853
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