Title :
High-Throughput LDPC Decoder for Long Code-Length
Author :
Ishikawa, Tatsuyuki ; Shimizu, Kazunori ; Ikenaga, Takeshi ; Goto, Satoshi
Author_Institution :
Graduate Sch. of Inf., Production & Syst., Waseda Univ., Fukuoka
Abstract :
We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates
Keywords :
iterative decoding; parity check codes; 69 MHz; LDPC decoder; iterative decoding; long code length; low density parity check codes; memory reduction method; Algorithm design and analysis; Error correction codes; Frequency; Hardware; Iterative algorithms; Iterative decoding; Parallel processing; Parity check codes; Production systems; Throughput;
Conference_Titel :
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0179-8
Electronic_ISBN :
1-4244-0180-1
DOI :
10.1109/VDAT.2006.258134
