Title :
A 1Mb CMOS DRAM with a divided bitline matrix architecture
Author :
Taylor, Russell ; Johnson, Mark
Author_Institution :
Mostek Corp., Carrollton, TX, USA
Abstract :
Application of a divided bitline matrix architecture, combined with a 1.2μ double metal CMOS process has resulted in the development of a 5V 1Mb DRAM with an array area to die ratio of 56.6%. Over 80% of the total die area is repairable using laser programmed redundant rows and columns.
Keywords :
CMOS process; Capacitance; Capacitors; Circuits; Decoding; Delay; Dielectric substrates; MOSFETs; Random access memory; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156856
