DocumentCode
2883261
Title
Clock-Jitter Reduction Techniques in Continuous Time Delta-Sigma Modulators
Author
Zare-Hoseini, Hashem ; Kale, Izzet
Author_Institution
Dept. of Electron. Syst., Westminster Univ., London
fYear
2006
fDate
26-28 April 2006
Firstpage
1
Lastpage
2
Abstract
This paper presents a brief overview and comparison of the most popular techniques used for suppressing the effect of clock-jitter in continuous-time delta-sigma modulators, including multi-bit, FIR, switched-capacitor, sine, and switched-shaped-current digital to analogue converters. Their principles and design issues are presented followed by a performance comparison which provides inform views on the power consumption issues, speed, ease of realization and effectiveness in jitter suppression of the various techniques
Keywords
clocks; delta-sigma modulation; jitter; switched capacitor networks; clock jitter reduction; continuous time delta-sigma modulators; digital to analogue converters; jitter suppression; switched capacitors converters; Clocks; Delta modulation; Digital modulation; Digital signal processing; Energy consumption; Finite impulse response filter; Jitter; Optical signal processing; Signal to noise ratio; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location
Hsinchu
Print_ISBN
1-4244-0179-8
Electronic_ISBN
1-4244-0180-1
Type
conf
DOI
10.1109/VDAT.2006.258138
Filename
4027510
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