Floorplanning Multiple Reticles for Multi-project Wafers

Author

Wu, Meng-Chiou ; Tsai, Shr-Cheng ; Lin, Rung-Bin

Author_Institution

Dept. of Comput. Sci. & Eng., Chung-li

fYear

2006

fDate

26-28 April 2006

Firstpage

1

Lastpage

4

Abstract

Floorplanning chips in more than one reticle for multi-project wafers has not been investigated. In this paper, we propose two approaches to this problem. We first formulate this problem with preselected reticle sizes as a mixed-integer linear programming (MILP) model. We then propose a compatibility-driven B*-tree dissection search (CBTDS) heuristic for it. Experiments for floorplanning chips in two reticles show that the MILP model is too complex to render good results, while CBTDS is very effective and efficient. Compared to a naive solution, CBTDS obtains a floorplan that uses 37% fewer wafers

Keywords

integer programming; integrated circuit layout; linear programming; reticles; tree searching; CBTDS heuristic; MILP model; compatibility-driven B*-tree dissection search; floorplanning chips; mixed-integer linear programming model; multiple reticles floorplanning; multiproject wafers; Blades; Chip scale packaging; Computer science; Costs; Design methodology; Hydrogen; Linear programming; Production; Semiconductor device measurement; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2006 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

1-4244-0179-8

Electronic_ISBN

1-4244-0180-1

Type

conf

DOI

10.1109/VDAT.2006.258145

Filename

4027517