DocumentCode :
2883379
Title :
Reliability and failure analysis of voting circuits in hardware redundant design
Author :
Radu, Mihaela ; Pitica, Dan ; Posteuca, Cristian
Author_Institution :
Fac. of Electron. & Telecommun., Tech. Univ. Cluj-Napoca, Romania
fYear :
2000
fDate :
2000
Firstpage :
421
Lastpage :
423
Abstract :
This paper presents some aspects of fault-tolerant design using hardware redundancy. The voter is the key element in N-modular redundant design. Hardware voters are bit voters that compute a majority of n input bits. An m-out-of-n hardware bit voter is a circuit with n bit inputs, and 1 bit output y, such that y=1 if at least m-out-of-n input bits have the value 1. A hardware voter can be implemented with logic gates in CMOS VLSI technology. Designers are looking for optimal designs with respect to the following criteria: circuit complexity, number of logic levels, fan-in and fan-out, power dissipation, testability, or any combinations of the previous requirements in order to obtain high reliability for the voting circuits. A detailed reliability analysis, failure modes and effects analysis of voters at the transistor level, is performed using CARE tools. CARE (computer aided reliability engineering) is a powerful software tool that can be used concurrently in the phases of R&D for complex reliability analysis of electronic circuits. The main goal of these analyses is to identify the best designs of voting circuits, in terms of reliability parameters and to identify the possible technological failures that can affect them
Keywords :
CMOS logic circuits; VLSI; circuit CAD; circuit complexity; circuit optimisation; computer aided engineering; design for testability; failure analysis; integrated circuit design; integrated circuit reliability; logic design; majority logic; redundancy; CARE tools; CMOS VLSI technology; N-modular redundant design; bit voters; circuit complexity; computer aided reliability engineering; electronic circuits; failure analysis; failure modes/effects analysis; fan-in; fan-out; fault-tolerant design; hardware redundancy; hardware redundant design; hardware voter; hardware voters; input bit majority; logic gates; logic levels; m-out-of-n hardware bit voter; optimal design; power dissipation; reliability; reliability analysis; reliability parameters; software tool; technological failures; testability; transistor level FMEA; voting circuit design; voting circuits; CMOS logic circuits; CMOS technology; Circuit testing; Failure analysis; Fault tolerance; Hardware; Logic testing; Performance analysis; Redundancy; Voting;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Materials and Packaging, 2000. (EMAP 2000). International Symposium on
Conference_Location :
Hong Kong
Print_ISBN :
0-7803-6654-9
Type :
conf
DOI :
10.1109/EMAP.2000.904192
Filename :
904192
Link To Document :
بازگشت