Title :
An Infrastructure IP for Repairing Multiple RAMs in SOCs
Author :
Huang, Chao-Da ; Tseng, Tsu-Wei ; Li, Jin-Fu
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jungli
Abstract :
Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories-based on TSMC 0.18mum standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%
Keywords :
fault diagnosis; integrated circuit testing; logic testing; random-access storage; redundancy; system-on-chip; 0.18 micron; infrastructure IP; multiple RAM; random-access storage; redundancy analysis; system-on-chips; Algorithm design and analysis; Built-in self-test; Circuit faults; Costs; Hardware; Performance evaluation; Random access memory; Read-write memory; Redundancy; Testing;
Conference_Titel :
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0179-8
Electronic_ISBN :
1-4244-0180-1
DOI :
10.1109/VDAT.2006.258150
