A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling

Author

Huang, Tsung-Chu ; Tzeng, Jing-Chi ; Chao, Yuan-Wei ; Chen, Ji-Jan ; Liu, Wei-Ting ; Lee, Kuen-Jong

Author_Institution

Dept. of Electron. Eng., Nat. Changhua Univ. of Educ.

fYear

2006

fDate

26-28 April 2006

Firstpage

1

Lastpage

4

Abstract

Power gating using sleep transistors is a trend for power management and test scheduling in the deep-submicron and even nanometer resolutions. This paper develops a sleep transistor allocation structure that can not only reduce the spike-time product with data retention but also balance the noise margins and timing in active mode. A switching activity based model is developed as a heuristics for sleep transistor clustering. Under the proposed model, the spike reduction can be up to 83% in average

Keywords

integrated circuit noise; integrated circuit testing; low-power electronics; switching circuits; transistor circuits; data retention; power management; sleep transistor allocation structure; sleep transistor clustering; spike reduction; supply-gating scheme; switching activity based model; test scheduling; Automatic testing; CMOS logic circuits; Circuit testing; Educational technology; Energy management; Power dissipation; Power system management; Scheduling; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2006 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

1-4244-0179-8

Electronic_ISBN

1-4244-0180-1

Type

conf

DOI

10.1109/VDAT.2006.258151

Filename

4027523