• DocumentCode
    2883469
  • Title

    A New Robust Paradigm for Diagnosing Hold-Time Faults in Scan Chains

  • Author

    Hsu, Edward ; Huang, Shi-Yu ; Tzeng, Chao-Wen

  • Author_Institution
    Yield Enhancement Service Sect. I, Taiwan Semicond. Manuf. Co.
  • fYear
    2006
  • fDate
    26-28 April 2006
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Hold-time violation is a common cause of failure at scan chains. A robust new paradigm for diagnosing such failure is presented in this paper. As compared to previous methods, the major advantage of ours is the ability to tolerate non-ideal conditions, e.g., under the presence of certain core logic faults or for those faults that manifest themselves intermittently. We first formulate the diagnosis problem as a delay insertion process. Then, two algorithms including a greedy algorithm and a so-called best-alignment based algorithm are proposed. Experimental results on a number of real designs are presented to demonstrate its effectiveness
  • Keywords
    boundary scan testing; delays; fault diagnosis; integrated circuit testing; best-alignment based algorithm; core logic faults; delay insertion process; greedy algorithm; hold-time fault diagnosis; hold-time violation; scan chains; Automatic test pattern generation; Circuit faults; Circuit testing; Delay; Flip-flops; Logic circuits; Logic design; Robustness; Sequential analysis; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation and Test, 2006 International Symposium on
  • Conference_Location
    Hsinchu
  • Print_ISBN
    1-4244-0179-8
  • Electronic_ISBN
    1-4244-0180-1
  • Type

    conf

  • DOI
    10.1109/VDAT.2006.258152
  • Filename
    4027524