Title :
An All-Digital Delay-Locked Loop for DDR SDRAM Controller Applications
Author :
Chung, Ching-Che ; Chen, Pao-Lung ; Lee, Chen-Yi
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
Abstract :
This paper presents an all-digital delay-locked loop (DLL) for DDR SDRAM controller applications. The presented all-digital, cell-based, DLL-based five-phase multi-phase clock generator can generate the required fixed timing delay (tSD) for DDR SDRAM controller to capture the output data (DQ) correctly. The proposed DLL-based multi-phase clock generator architecture can lock to the harmonic of input clock period and still get a correct multi-phase clock output. Hence the design challenges to build a high resolution delay line with minimum intrinsic delay can be reduced. Simulation results and chip measurement results show that the proposed DLL can generate desired tSD delay with error < 7.6%. The power consumption of the proposed DLL is 4.1mW (at DDR-200) and is 9.0mW (at DDR-400)
Keywords :
DRAM chips; SRAM chips; clocks; delay lines; delay lock loops; 4.1 mW; 9.0 mW; DDR SDRAM controller; all-digital delay-locked loop; fixed timing delay; high resolution delay line; multiphase clock generator; multiphase clock output; Circuit noise; Clocks; DRAM chips; Delay lines; Energy consumption; Frequency; Jitter; Phase locked loops; Phase noise; Timing;
Conference_Titel :
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0179-8
Electronic_ISBN :
1-4244-0180-1
DOI :
10.1109/VDAT.2006.258159