• DocumentCode
    2883766
  • Title

    Memory-Hierarchy-Based Power Reduction for H. 264/AVC Video Decoder

  • Author

    Liu, Tsu-Ming ; Lee, Chen-Yi

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
  • fYear
    2006
  • fDate
    26-28 April 2006
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Memory storage is crucial power factor in H.264/AVC video decoding system. In this paper, we exploit three-level of memory hierarchy to break the data dependency and reduce the number of access for external memory. Further, we apply line-pixel-lookahead (LPL) scheme to make a compromise between power consumption and internal memory cost. Experimental results prove that about 50% of memory power reduction can be achieved as compared to comparable decoders without exploiting memory hierarchy (To Wei Chen et al., 2005 and Hu et al., 2004)
  • Keywords
    DRAM chips; file organisation; video coding; H.264/AVC video decoder; data dependency; line-pixel-lookahead scheme; memory storage; memory-hierarchy; video decoding system; Automatic voltage control; Costs; Decoding; Energy consumption; Power engineering and energy; Random access memory; Reactive power; Registers; SDRAM; Video compression;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation and Test, 2006 International Symposium on
  • Conference_Location
    Hsinchu
  • Print_ISBN
    1-4244-0179-8
  • Electronic_ISBN
    1-4244-0180-1
  • Type

    conf

  • DOI
    10.1109/VDAT.2006.258171
  • Filename
    4027543