Title :
A CMOS 32b Wallace tree multiplier-accumulator
Author :
El-Gamal, A. ; Gluss, D. ; Greene, J. ; Reyneri, J. ; Peng-Huat Ang
Author_Institution :
LSI Logic Systems Research Laboratory, Palo Alto, CA, USA
Abstract :
A 32b integer multiplier-accumulator chip with 56ns cycle time will be described. Automated placement, routing and cell compilation was used on a 2μm CMOS IC which dissipates 1W.
Keywords :
Adders; Algorithm design and analysis; Application specific integrated circuits; CMOS logic circuits; Design optimization; Integrated circuit interconnections; Large scale integration; Libraries; Propagation delay; Signal design;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156889
