A Low Power, Transverse Analog FIR Filter as Feed Forward Equalizer in Gigabit Ethernet

Author

Vahidfar, M.B. ; Shoaei, O. ; Fardis, M.

Author_Institution

Dept. of Electr. & Comput. Eng., Tehran Univ.

fYear

2006

fDate

26-28 April 2006

Firstpage

1

Lastpage

4

Abstract

A low power analog feedforward error equalizer (AFFE) is presented in this paper that cancels precursor inter symbol interferences (ISI) in the front end of gigabit Ethernet on twisted pair interfaces. Forward equalizing in analog domain is beneficial due to consuming lower power and silicon area comparing to digital forward equalizers. Moreover it leads to higher speed which is demanded for real time equalization and also less equalizer complexity. The proposed equalizer is a five tap discrete time filter which is designed in a 0.18mum CMOS technology. The design operates at 125MHz while consuming 42mW from a 1.8V supply. Each filter taps is implemented by an improved Gilbert cell instead of using a multiplier for each bit of the filter tap. Moreover S/H power and speed requirements are relaxed by using redundant S/H´s and additional clocking phase

Keywords

CMOS analogue integrated circuits; FIR filters; equalisers; feedforward; intersymbol interference; local area networks; low-power electronics; 0.18 micron; 1.8 V; 125 MHz; 42 mW; CMOS technology; Gilbert cell; analog FIR filter; analog feedforward error equalizer; discrete time filter; forward equalizing; gigabit Ethernet; intersymbol interferences; low power filter; CMOS technology; Clocks; Copper; Crosstalk; Decision feedback equalizers; Ethernet networks; Feeds; Finite impulse response filter; Intersymbol interference; Pulse modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2006 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

1-4244-0179-8

Electronic_ISBN

1-4244-0180-1

Type

conf

DOI

10.1109/VDAT.2006.258177

Filename

4027549