Title :
A 13ns/500mW 64Kb ECL RAM
Author :
Ogiue, K. ; Odaka, M. ; Miyaoka, Shin´ichiro ; Masuda, I. ; Ikeda, Takashi ; Tonomura, K. ; Ohba, Tsuyoshi
Author_Institution :
Hitachi Device Development Center, Tokyo, Japan
Abstract :
This paper will cover the design of a 16K×4 SRAM which uses buried twin-well 2μm CMOS transistors and 4GHz cutoff frequency bipolar transistors. The circuit combines a high-resistance polysilicon - load NMOS memory cell with mixed MOS/bipolar periphery circuits to achieve ECL compatibility, 13ns access times and an operating power of 500mW at 40MHz.
Keywords :
Bipolar transistors; CMOS technology; Capacitance; Cutoff frequency; Decoding; Driver circuits; Pins; Power dissipation; Random access memory; Read-write memory;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156897
