High quality ultra thin CVD HfO/sub 2/ gate stack with poly-Si gate electrode

Author

Lee, S.J. ; Luan, H.F. ; Bai, W.P. ; Lee, C.H. ; Jeon, T.S. ; Senzaki, Y. ; Roberts, D. ; Kwong, D.L.

Author_Institution

Microelectron. Res. Center, Texas Univ., Austin, TX, USA

fYear

2000

fDate

10-13 Dec. 2000

Firstpage

31

Lastpage

34

Abstract

We have developed and demonstrated an in-situ rapid thermal CVD (RTCVD) process for the fabrication of high quality ultra thin CVD HfO/sub 2/ gate stack that is compatible with conventional self-aligned poly-Si gate technology. These poly-Si gated HfO/sub 2/ gate stack show excellent interface properties, EOT=10.4 /spl Aring/, and leakage current Jg=0.23 mA/cm/sup 2/ @Vg=-1 V which is several orders of magnitude lower than RTO SiO/sub 2/ with poly-Si gate. In addition, the HfO/sub 2/ gate stack is thermally stable in direct contact with n/sup +/-poly Si gate under typical dopant activation conditions. These films also show excellent reliability under high-field electrical stress. We have also fabricated and demonstrated NMOSFETs, and studied boron penetration in HfO/sub 2/ gate stack with p/sup +/-poly Si gate.

Keywords

CVD coatings; MOSFET; dielectric thin films; hafnium compounds; rapid thermal processing; HfO/sub 2/-Si; NMOSFET; boron penetration; dielectric film; dopant activation; equivalent oxide thickness; fabrication; high field electrical stress; interface properties; leakage current; polysilicon gate electrode; rapid thermal CVD; reliability; self-aligned technology; thermal stability; ultrathin HfO/sub 2/ gate stack; Annealing; Boron; CMOS technology; Electrodes; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFETs; Thermal stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-6438-4

Type

conf

DOI

10.1109/IEDM.2000.904252

Filename

904252