Title :
Yield statistics for large area ICs
Author_Institution :
IBM General Technology Division, Essex Junction, VT, USA
Abstract :
This report will cover an examination of Poisson statistics and their inadequacy to represent defects in large area chips on a wafer. Measurements of defects will be cited and the consequences on redundancy methods will be discussed.
Keywords :
Analysis of variance; Instruments; Integrated circuit technology; Integrated circuit yield; Manufacturing processes; Redundancy; Semiconductor device modeling; Statistical distributions; Statistics; Wafer scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156918
