• DocumentCode
    2884350
  • Title

    A 15ns CMOS 64K RAM

  • Author

    Shuster, Samuel ; Chappel, B. ; Franch, Robert ; Grier, P. ; Klepner, S. ; Lai, Jih-Sheng ; Lipa, R. ; Perry, R. ; Pokorny, W. ; Roberge, M.

  • Author_Institution
    IBM Research Center, Yorktown Heights, NY, USA
  • Volume
    XXIX
  • fYear
    1986
  • fDate
    19-21 Feb. 1986
  • Firstpage
    206
  • Lastpage
    207
  • Abstract
    A 64K CMOS clocked SRAM which attains an access time of 15ns through the use of 1.3μm CMOS with self-aligned TiSi2technology will be presented. Physical design of the chip was performed using a ground rule independent layout program.
  • Keywords
    CMOS memory circuits; CMOS process; CMOS technology; Decoding; Delay; MOS devices; Random access memory; Read-write memory; Silicides; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
  • Conference_Location
    Anaheim, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1986.1156919
  • Filename
    1156919
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2884350