Title :
A 15ns CMOS 64K RAM
Author :
Shuster, Samuel ; Chappel, B. ; Franch, Robert ; Grier, P. ; Klepner, S. ; Lai, Jih-Sheng ; Lipa, R. ; Perry, R. ; Pokorny, W. ; Roberge, M.
Author_Institution :
IBM Research Center, Yorktown Heights, NY, USA
Abstract :
A 64K CMOS clocked SRAM which attains an access time of 15ns through the use of 1.3μm CMOS with self-aligned TiSi2technology will be presented. Physical design of the chip was performed using a ground rule independent layout program.
Keywords :
CMOS memory circuits; CMOS process; CMOS technology; Decoding; Delay; MOS devices; Random access memory; Read-write memory; Silicides; Timing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156919
