FFT implementation on DSP-chips-theory and practice

Author

Meyer, R. ; Schwarz, K.

Author_Institution

Lehrstuhl fuer Nachrichtentech., Erlangen-Nurnberg Univ., West Germany

fYear

1990

fDate

3-6 Apr 1990

Firstpage

1503

Abstract

The problem of comparing different algorithms for the execution of the fast Fourier transform (FFT) is considered. Instead of counting the required arithmetic operations, the necessary number of instruction cycles for an FFT implementation on different digital signal processors (DSPs) is used as a measure. It turns out that this more practical figure of merit yields a rather different valuation of the algorithms. Furthermore, a method to halve the table size for the radix-2 twiddle factors is described. Some new FFT programs for execution on DSPs are compared with programs provided by the manufacturers

Keywords

digital arithmetic; digital signal processing chips; fast Fourier transforms; DSP chips; FFT; FFT programs; digital signal processors; fast Fourier transform; instruction cycles; radix-2 twiddle factors; Algorithm design and analysis; Computer architecture; Cost accounting; Digital arithmetic; Digital signal processing; Digital signal processors; Fast Fourier transforms; Flexible printed circuits; Manufacturing; Signal processing algorithms; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on

Conference_Location

Albuquerque, NM

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1990.115692

Filename

115692