Title :
A basic-cell buffer 440K-transistor CMOS masterslice
Author :
Arakawa, Takeshi ; Ueda, Makoto ; Saito, Yuya ; Fujimura, Takashi ; Asai, Satoshi ; Terai, M. ; Akasaka, Y. ; Kuramitsu, Y.
Author_Institution :
Mitsubishi LSI Res.-Dev. Laboratory, Itami, Japan
Abstract :
A masterslice containing 437,976 transistors on a 12.7×11.96mm2chip and employing a gate-isolation concept with no fixed routing tracks and no dedicated buffers, will be reported. The masterslice has been fabricated in 1.3μm CMOS technology. A 13MHz facsimile processor has been implemented using this array.
Keywords :
Art; CMOS technology; Circuit testing; Laboratories; Large scale integration; Logic gates; Logic testing; Propagation delay; Read only memory; Read-write memory;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156920
