SOA improvement by a double RESURF LDMOS technique in a power IC technology

Author

Parthasarathy, V. ; Khemka, V. ; Zhu, R. ; Bose, A.

Author_Institution

Semicond. Products Sector, Motorola Inc., Mesa, AZ, USA

fYear

2000

fDate

10-13 Dec. 2000

Firstpage

75

Lastpage

78

Abstract

This paper presents a technique that provides double RESURF action in a lateral power MOSFET controlled through an independently biased terminal thereby realizing a two-fold improvement in electrical static SOA over single RESURF lateral device structures at high drain voltages. The technique has been successfully implemented to realize a high-side capable lateral power MOSFET with BV/sub dss/ of 61 V and specific on-resistance (R/sub dson/A) of 0.54 m/spl Omega/-cm/sup 2/ and with a maximum electrical static operating current of 1.9 A/cm at a drain to source voltage of 54 V.

Keywords

MOS integrated circuits; integrated circuit technology; power MOSFET; power integrated circuits; semiconductor device breakdown; 61 V; breakdown voltage; double RESURF LDMOS technique; electrical static operating current; lateral power MOSFET; power IC technology; safe operating area; specific on-resistance; Application software; Automotive engineering; Computer peripherals; Doping; Kirk field collapse effect; MOSFET circuits; Power MOSFET; Power integrated circuits; Semiconductor optical amplifiers; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-6438-4

Type

conf

DOI

10.1109/IEDM.2000.904262

Filename

904262