Title :
Architecture for DSP VLSI
Author_Institution :
Texas Instruments, Inc., Houston, TX, USA
Abstract :
AS CMOS technology scales to 1μm, it is becoming possible to integrate more than 500K transistors on a processor-like chip. At this point, various digital signal processing (DSP) chip architecture approaches need to be re-examined to enable VLSI designers to obtain on optimal solution for system designers in terms of performance, power, cost, flexibility and development time. The panel will explore and debate several DSP architectural options available to VLSI designers, such as single-processor, systolic arrays, parallel processors, customs, etc.
Keywords :
Architecture; Costs; Digital signal processing; Digital signal processing chips; History; Instruments; Modems; Pipeline processing; Signal processing algorithms; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156931