Title :
A 4b × 4b multiplier and 3b counter in Josephson threshold logic
Author :
Hatano, Y. ; Harada, Y. ; Yamashita, Katsumi ; Kawabe, U.
Author_Institution :
Hitachi Central Research Laboratory, Tokyo, Japan
Abstract :
This Paper will report on the development of a 4×4b parallel multiplier with a carry-to-carry delay time of 279ps and a 3b binary counter operating at 2.2 GHz implemented in Josephson junction technology.
Keywords :
Adders; Counting circuits; Current measurement; DC generators; Josephson junctions; Large scale integration; Magnetic circuits; Power amplifiers; Power generation; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156938
