Title :
A 0.9ns ECL 16 × 4 register file
Author :
Chang, David ; Schmitz, C. ; Hingarh, H. ; Bakker, Gregory
Author_Institution :
Fairchild Research Center, Palo Alto, CA, USA
Abstract :
This paper will describe a 16×4 ECL register file featuring an address access time of 0.9ns and power dissipation of 400mW. Performance has been achieved by using a fully self-aligned poly bipolar technology with trench isolation.
Keywords :
Capacitance; Circuit synthesis; Decoding; Delay; Geometry; Pulsed power supplies; Registers; Solid state circuits; Temperature; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156943
