• DocumentCode
    2884755
  • Title

    A 0.9ns ECL 16 × 4 register file

  • Author

    Chang, David ; Schmitz, C. ; Hingarh, H. ; Bakker, Gregory

  • Author_Institution
    Fairchild Research Center, Palo Alto, CA, USA
  • Volume
    XXIX
  • fYear
    1986
  • fDate
    19-21 Feb. 1986
  • Firstpage
    188
  • Lastpage
    189
  • Abstract
    This paper will describe a 16×4 ECL register file featuring an address access time of 0.9ns and power dissipation of 400mW. Performance has been achieved by using a fully self-aligned poly bipolar technology with trench isolation.
  • Keywords
    Capacitance; Circuit synthesis; Decoding; Delay; Geometry; Pulsed power supplies; Registers; Solid state circuits; Temperature; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
  • Conference_Location
    Anaheim, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1986.1156943
  • Filename
    1156943
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2884755