Title :
A 47ns 64KW × 4b CMOS DRAM with relaxed timing requirements
Author :
Kobayashi, Takehiko ; Arimoto, Keisuke ; Ikeda, Yasuhiro ; Hatanaka, M. ; Mashiko, K. ; Yamada, Makoto
Author_Institution :
Mitsubishi LSI Research and Development Laboratory, Itami, Japan
Abstract :
A 256Kb DRAM which eliminates the positive-going RAS signal edge from the internal timing by a time-out function, will be reported. The access time is 47ns with predecoding, and power dissipation is 115mW at 200ns cycle time.
Keywords :
CMOS process; Capacitance; Clocks; Decoding; Pulse circuits; Random access memory; Read-write memory; Space vector pulse width modulation; Switches; Timing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156944
