Three dimensional CMOS integrated circuits on large grain polysilicon films

Author

Chan, V.W.C. ; Chan, P.C.H. ; Chan, M.

Author_Institution

Hong Kong Univ. of Sci. & Technol., Clear Water Bay, China

fYear

2000

fDate

10-13 Dec. 2000

Firstpage

161

Lastpage

164

Abstract

In this paper, we report high performance three-dimensional (3-D) CMOS integrated circuits. The first layer of transistors is fabricated on Silicon-on-Insulator (SOI) and second layer is fabricated on large-grain polysilicon-on-insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of amorphous silicon through metal-induced lateral crystallization (MILC) at an elevated temperature. Compared with the conventional 2-D CMOS SOI low-voltage circuit, 3D circuit shows significant reduction in circuit area, shorter propagation delay and lower dynamic power consumption.

Keywords

CMOS integrated circuits; elemental semiconductors; grain size; low-power electronics; recrystallisation; semiconductor thin films; silicon; silicon-on-insulator; LPSOI; SOI; Si; circuit area; large-grain polysilicon film; low-voltage circuit; metal-induced lateral crystallization; propagation delay; recrystallization; three-dimensional CMOS integrated circuit; Amorphous silicon; CMOS integrated circuits; CMOS technology; Crystallization; Energy consumption; Grain size; MOSFETs; Semiconductor films; Silicon on insulator technology; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-6438-4

Type

conf

DOI

10.1109/IEDM.2000.904283

Filename

904283