Title :
Circuit analysis of the memristive stateful implication gate
Author :
Xudong Fang ; Yuhua Tang
Author_Institution :
Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
fDate :
September 26 2013
Abstract :
A recently published memristive stateful implication (IMP) gate circuit is analysed with confirmation that it cannot achieve the full resistance switching of the output memristor in case both input memristors of the IMP gate are in the OFF resistance state. The initial parameter conditions for the IMP gate are derived, and the minimum resistance of the output memristor achievable is yielded. The HSPICE simulation confirms that a resistance refreshing scheme is indispensable for the IMP gate to function properly.
Keywords :
logic gates; memristors; network analysis; HSPICE simulation; OFF resistance state; circuit analysis; memristive stateful implication gate; output memristor; resistance refreshing scheme; resistance switching;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2013.2140
