Title :
Three-dimensional shared memory fabricated using wafer stacking technology
Author :
Lee, K.W. ; Nakamura, T. ; Ono, T. ; Yamada, Y. ; Mizukusa, T. ; Hashimoto, H. ; Park, K.T. ; Kurino, H. ; Koyanagi, M.
Author_Institution :
Dept. of Machine Intelligence & Syst. Eng., Tohoku Univ., Sendai, Japan
Abstract :
We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.
Keywords :
integrated circuit technology; integrated memory circuits; parallel processing; shared memory systems; broadcast operation; fabrication; parallel processor; shared memory chip; test circuit; three-dimensional integration technology; wafer stacking method; Broadcasting; Fabrication; Machine intelligence; Parallel processing; Random access memory; Read-write memory; Stacking; Systems engineering and theory; Testing; Wafer bonding;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904284
