DocumentCode :
2884918
Title :
A 4Mb DRAM with cross point trench transistor cell
Author :
Shah, Aamer ; Chu-Ping Wang ; Womack, R. ; Gallia, J. ; Shichijo, H. ; Davis, Howard ; Elahy, M. ; Banerjee, Sean ; Pollack, G. ; Richardson, William ; Bordelon, D. ; Malhi, S. ; Pilch, C. ; Bao Tran ; Chatterjee, Parag
Author_Institution :
Texas Instruments Inc., Dallas, TX, USA
Volume :
XXIX
fYear :
1986
fDate :
19-21 Feb. 1986
Firstpage :
268
Lastpage :
269
Abstract :
This report will describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm2. Row and static column access times are 170ns and 30ns, respectively.
Keywords :
CMOS process; CMOS technology; Deafness; Decoding; Driver circuits; Instruments; Log periodic antennas; Plugs; Random access memory; Vehicles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
Type :
conf
DOI :
10.1109/ISSCC.1986.1156951
Filename :
1156951
Link To Document :
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