Title :
A 18ns 8KW × 9b NMOS RAM
Author :
Segawa, Masaya ; Ariizumi, S. ; Suzuki, Yuya ; Kondo, Toshiaki ; Ando, Takehiro ; Ochii, K. ; Masuoka, Fujio
Author_Institution :
Toshiba Integrated Circuit Division, Kawasaki, Japan
Abstract :
An 8K×9 NMOS SRAM using a shared-word line and one-eighth activated row decoder circuit, achieving 18ns access times and 500mW active power dissipation, will be reported. The SRAM was fabricated in 1.5μm double-poly, double-metal process.
Keywords :
Aluminum; Decoding; Energy consumption; Equalizers; Logic circuits; MOS devices; Packaging; Power dissipation; Random access memory; Read-write memory;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156954
