• DocumentCode
    2884952
  • Title

    A 18ns 8KW × 9b NMOS RAM

  • Author

    Segawa, Masaya ; Ariizumi, S. ; Suzuki, Yuya ; Kondo, Toshiaki ; Ando, Takehiro ; Ochii, K. ; Masuoka, Fujio

  • Author_Institution
    Toshiba Integrated Circuit Division, Kawasaki, Japan
  • Volume
    XXIX
  • fYear
    1986
  • fDate
    19-21 Feb. 1986
  • Firstpage
    202
  • Lastpage
    203
  • Abstract
    An 8K×9 NMOS SRAM using a shared-word line and one-eighth activated row decoder circuit, achieving 18ns access times and 500mW active power dissipation, will be reported. The SRAM was fabricated in 1.5μm double-poly, double-metal process.
  • Keywords
    Aluminum; Decoding; Energy consumption; Equalizers; Logic circuits; MOS devices; Packaging; Power dissipation; Random access memory; Read-write memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
  • Conference_Location
    Anaheim, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1986.1156954
  • Filename
    1156954
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2884952