DocumentCode :
2884973
Title :
A 36/72b CMOS micro-mainframe chip set
Author :
Fier, D. ; Caulk, R. ; Torgerson, P. ; Breid, D. ; Bradley, Richard ; LeClair, K.
Author_Institution :
Sperry Micro Products Development, Eagan, MN, USA
Volume :
XXIX
fYear :
1986
fDate :
19-21 Feb. 1986
Firstpage :
26
Lastpage :
27
Abstract :
A six-chip processor set with mainframe compatible instructions, containing 786,000 transistors, fabricated with a 
m double-layer metal technology, will be described. The chip set can be configured to operate from 0.4 to 1.5MIPS.
m double-layer metal technology, will be described. The chip set can be configured to operate from 0.4 to 1.5MIPS.Keywords :
Architecture; Automatic testing; CMOS process; Libraries; Logic; Pins; Product development; Read only memory; Software testing; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
Type :
conf
DOI :
10.1109/ISSCC.1986.1156955
Filename :
1156955
Link To Document :
