Title :
80 nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process
Author :
Sayama, H. ; Nishida, Y. ; Oda, H. ; Tsuchimoto, J. ; Umeda, H. ; Teramoto, A. ; Eikyu, K. ; Inoue, Y. ; Inuishi, M.
Author_Institution :
ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
Double offset-implanted source/drain extension and 550/spl deg/C silicon nitride deposition for sidewall and borderless contact have been applied to sub-0.1 /spl mu/m CMOS for improvement of short channel effect as well as parasitic resistance. Consequently, 830/400 /spl mu/A//spl mu/m drive current with 2.5 nm gate insulator has been achieved under 1 nA//spl mu/m off-leakage at 1.5 V operation with short channel tolerance to 80 nm gate length.
Keywords :
CMOS integrated circuits; MOSFET; chemical vapour deposition; etching; ion implantation; rapid thermal annealing; 1.5 V; 80 nm; CMOSFET technology; CVD oxide film; SiN; activation RTA; borderless contact; double offset-implanted source/drain extension; drive current; etch back; hot carrier endurance; low temperature SiN process; off-leakage; short channel tolerance; short-channel effect; sidewall spacer; CMOS process; CMOS technology; CMOSFETs; Electrodes; Etching; Fabrication; Heat treatment; Insulation; Silicon compounds; Temperature;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904301
