Title :
Process design methodology for via-shape-controlled, copper dual-damascene interconnects in low-k organic film
Author :
Kinoshita, K. ; Tada, M. ; Usami, T. ; Hiroi, M. ; Tonegawa, T. ; Shiba, K. ; Onodera, T. ; Tagami, M. ; Saitoh, S. ; Hayashi, Y.
Author_Institution :
Syst. Devices & Fundamental Res., NEC Corp., Sagamihara, Japan
Abstract :
By dual hard mask (dHM) process combined with sidewall-hardening etching step, copper dual-damascene (DD) interconnects are fabricated in low-k organic film without any etch-stop layers under the trench. Careful designs of dHM structures and their patterning sequence enable us to harden the via-sidewall by fluorocarbon plasma, which is a key to reduce final via-shoulder loss at the via/trench connecting region. The low-k structure has low via resistance such as 0.65 /spl Omega//0.28 /spl mu/m/sup /spl phi//-via while keeping the large tolerance of misalignment in via/trench, appreciable for 0.1 /spl mu/m-generation CMOS ULSIs.
Keywords :
CMOS integrated circuits; ULSI; copper; delays; dielectric thin films; integrated circuit interconnections; masks; sputter etching; 0.1 micron; CMOS; Cu; ULSI; dual hard mask process; dual-damascene interconnects; fluorocarbon plasma hardening; low-k organic film; misalignment; patterning sequence; process design methodology; sidewall-hardening etching step; via shape control; via-shoulder loss; via/trench connecting region; Capacitance; Copper; Etching; Hydrogen; Joining processes; National electric code; Plasma applications; Process design; Silicon compounds; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904305
