Title :
A CMOS macro array
Author :
Kitamura, Yoshifumi ; Furuki, Kenji ; Minowa, Masanao ; Yamada, Tomoaki
Author_Institution :
NEC LSI Development Division, Kawasaki, Japan
Abstract :
A 1.6μm, 2-level netal, N-well logic array, containing gate array and PLA cells will be reported. The performance and area for a 16b ALU and 16b up-down counter will be compared with a conventional gate array implementation.
Keywords :
CMOS logic circuits; Counting circuits; Logic arrays; Logic gates; Programmable logic arrays;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156974
