Title :
A 16ns CMOS EEPLA with reprogrammable architecture
Author :
Rutledge, D. ; Turner, Jessica ; Darling, Robert ; Josephson, G.
Author_Institution :
Lattice Semiconductor Corp., Hillsboro, OR, USA
Abstract :
A PLA, whose architecture may be electrically programmed, will be described. The device has been built in 1.2μm EEPROM technology and operates at 20MHz with 380mW dissipation. On-chip scan diagnostics are used for testing.
Keywords :
Capacitance; Circuit testing; Clocks; EPROM; Logic devices; Logic testing; Parallel programming; Programmable logic arrays; Registers; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156977
