Title :
A low voltage high unity-gain bandwidth CMOS op-amp
Author :
Yu, Chih-Min ; Lin, Zhi-Ming ; Chen, Jun-Da
Author_Institution :
Dept. of Electr. Eng., Nat. Changhua Univ. of Educ., Taiwan
Abstract :
This work presents a ±1V CMOS operation amplifier with constant-gm rail-to-rail input stage and class-AB output stage. The designed op-amp has been implemented in TSMC 2P4M 0.35 μm CMOS technology and simulated by Hspice. The unity-gain bandwidth of the op-amp is 13.1 MHz with Miller compensation. The slew-rate and settling time are 24V/μs and 0.48 μs, respectively. The open loop gain is 108 dB with 58 degree phase margin.
Keywords :
CMOS analogue integrated circuits; low-power electronics; operational amplifiers; 0.35 micron; 0.48 mus; 108 dB; 13.1 MHz; CMOS operation amplifier; Hspice simulation; Miller compensation; TSMC 2P4M technology; class-AB output stage; high unity-gain bandwidth CMOS op-amp; low voltage op-amp; open loop gain; rail-to-rail input stage; settling time; slew-rate; Analog circuits; Bandwidth; CMOS analog integrated circuits; CMOS technology; Circuit simulation; Gain; Low voltage; Operational amplifiers; Rail to rail amplifiers; Rail to rail inputs;
Conference_Titel :
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8660-4
DOI :
10.1109/APCCAS.2004.1412687
