DocumentCode
2885418
Title
An 8MIPS CMOS digital signal processor
Author
van Meerbergen, J. ; Welten, F. ; Wijk, F.v. ; Stoter, J. ; Huisken, J. ; Delaruelle, A. ; Eerdewijk, K.V. ; Schmid, J. ; Wittek, J.
Author_Institution
Philips Research Laboratories, Eindhoven, Netherlands
Volume
XXIX
fYear
1986
fDate
19-21 Feb. 1986
Firstpage
84
Lastpage
85
Abstract
A 2μm digital signal processor with a 125ns instruction cycle will be described. It contains two 16b data buses, executes a 40b orthogonal instruction set and supports up to six concurrent arithmetic and data-move operations in each instruction.
Keywords
Arithmetic; CMOS process; Data buses; Digital signal processors; Hardware; Pipelines; Random access memory; Read only memory; Read-write memory; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location
Anaheim, CA, USA
Type
conf
DOI
10.1109/ISSCC.1986.1156982
Filename
1156982
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