Title :
A pattern matching processor array with defect tolerance
Author :
Kawada, T. ; Takahashi, Y. ; Tsuda, Naoaki ; Waki, Masaki ; Hagiwara, Naoki
Author_Institution :
NTT Electrical Communication Laboratories, Tokyo, Japan
Abstract :
A 16b processor chip with sorter and 32Kb dictionary RAM has been developed for hand-printed Kanji character recognition. This paper will describe the design techniques used to achieve defect tolerance in the memory and logic blocks. A 18.5×20.5mm2chip contains 460,000 transistors using a 3μm double metal CMOS technology.
Keywords :
Circuit testing; Dictionaries; Hardware; Logic circuits; Optical character recognition software; Pattern matching; Performance evaluation; Portable media players; Registers; Switching circuits;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156985
