A new approach to optimal transistor sizing in CMOS digital designs

The authors present a new method of transistor sizing, in which the mathematical method is used for sizing of critical paths and the heuristic method is used for desizing of non-critical paths. The distributed RC delay model is used in the delay calculation, and the active transistor area is used in the area calculation. In order to reduce the overall problem dimension, a basic block called an extended stage is introduced which includes a basic stage, parallel transistors and a complementary part. Optimization for multiple critical paths is formulated as a problem of area minimization subject to delay constraints and is solved by the augmented Lagrange multiplier method. The transistor sizes along non-critical paths are decreased successively without affecting the critical path delay times. The proposed scheme was successfully applied to several test circuits